As manufacturing of complementary-metal-oxide-semiconductor (CMOS) transistors continues to scale, resistance at interfaces of source/drain (S/D) and silicide formed thereupon becomes more and more a dominant factor or contributor towards the overall external parasitic resistance. As S/D contact dimensions are further scaled, conventional approaches and/or methods are no longer capable of handling interface resistance.
There are several approaches and/or methods being recently developed in order to achieve lower contact resistance at the source and/or drain of n-type and/or p-type transistors. Ion implantation into the silicide region is one approach and forming dual silicide is another approach. However, these approaches all require additional masks and complicated integration scheme associated therewith. For example, these two approaches require the formation of soft/hard masks. Additionally, together with the formation of these masks, there is difficulty in the removal of these masks in small contact opening areas.